Scheduling semiconductor final testing a DBR based simulation model

IC testing is carried out in the make-to-order mode upon the testing route arrangement according to clients´ demand, without the need for materials. Different testing routes are adopted for the order according to clients´ demands or product features. Lin et al. probed into this topic on the assumption that the testing flow for each order is the same and with the logic IC testing as the object for discussion, thus the customized route demand cannot be satisfied. This study focuses on the actual working mode of memory IC, and summarizes several kinds of work flows. The testing time for each station is different, and there are two types of resource constraints on the testing route: 1) non-identical parallel machines, which are fast or slow according to the testing efficiency; 2) burn-in machines, which are a few in numbers and have a long working time. This study aims to develop a MDD (Match Due Date) scheduling by utilizing the characteristics of Drum-Buffer-Rope and the heuristic scheduling. The purpose of scheduling is to reduce earliness, reduce tardiness, make less the number of setups, shorten the flow time and enhance the CLIP (confirmed line item performance). Desirability function is used to integrate five performance indicators for evaluating the performance. The results of the simulation experiments show that, the MDD scheduling developed by this study has better performance than conventional dispatching rules (e.g. SPT, EDD).