• DocumentCode
    1652829
  • Title

    A guiding coverage metric for formal verification

  • Author

    Haedicke, Finn ; Grosse, Daniel ; Drechsler, Rolf

  • Author_Institution
    Inst. of Comput. Sci., Univ. of Bremen, Bremen, Germany
  • fYear
    2012
  • Firstpage
    617
  • Lastpage
    622
  • Abstract
    Considerable effort is made to verify the correct functional behavior of circuits and systems. To guarantee the overall success metric-driven verification flows have been developed. In these flows coverage metrics are omnipresent. Well established coverage metrics for simulation-based verification approaches exist. This is however not the case for formal verification where property checking is a major technique to prove the correctness of the implementation. In this paper we present a guiding coverage metric for this formal verification setting. Our metric reports a single number describing how much of the circuit behavior is uniquely determined by the properties. In addition, the coverage metric guides the verification engineer to achieve completeness by providing helpful information about missing scenarios. This information comes from a new behavior classification algorithm which determines uncovered behavior classes for a signal and allows to compute the coverage of a signal. To measure the complete circuit behavior we devise a coverage metric for a set of signals. The metric is calculated by partitioning the coverage computation into a safe part and an unsafe part where the latter one is weighted accordingly using recursion. This procedure takes into account that in practice properties refer to internal signals which in turn need to be covered them-self. Overall, our metric allows to track the verification progress in property checking and significantly aid the verification engineers in completing the property set.
  • Keywords
    circuit analysis computing; formal verification; logic design; pattern classification; behavior classification algorithm; circuit behavior; circuit functional behavior; coverage computation partitioning; formal verification; guiding coverage metrics; metric-driven verification flows; property checking; simulation-based verification approaches; system functional behavior; uncovered behavior class determination; verification engineer; Algorithm design and analysis; Classification algorithms; Integrated circuit modeling; Measurement; Memory management; Multiplexing; Upper bound;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012
  • Conference_Location
    Dresden
  • ISSN
    1530-1591
  • Print_ISBN
    978-1-4577-2145-8
  • Type

    conf

  • DOI
    10.1109/DATE.2012.6176546
  • Filename
    6176546