DocumentCode :
1652848
Title :
Platform-Based Resource Binding Using a Distributed Register-File Microarchitecture
Author :
Cong, Jason ; Fan, Yiping ; Jiang, Wei
Author_Institution :
Dept. of Comput. Sci., California Univ., Los Angeles, CA
fYear :
2006
Firstpage :
709
Lastpage :
715
Abstract :
Behavior synthesis and optimization beyond the register transfer level require an efficient utilization of the underlying platform features. This paper presents a platform-based resource-binding approach using a distributed register-file microarchitecture (DRFM) that makes efficient use of distributed embedded memory blocks as register files in modern FPGAs. A DRFM contains multiple islands, each having a local register file, a functional unit pool and data-routing logic. Compared with the traditional discrete-register counterpart, a DRFM allows use of the platform-featured on-chip memory or register-file IP blocks to implement its local register files, and this results in substantial saving of multiplexing logic and global interconnects. DRFM provides a useful architectural template and a direct optimization objective for minimizing inter-island connections for synthesis algorithms. Based on DRFM, we propose a novel binding algorithm focusing on the minimization of the inter-island connections. By applying our approach, significant reductions on multiplexors and global-interconnections are observed. On the Xilinx Virtex II FPGA platform, our experimental results show a 2times logic area reduction and a 7.8% performance improvement, compared with the traditional discrete-register-based approach
Keywords :
field programmable gate arrays; memory architecture; multiplexing; Xilinx Virtex II FPGA platform; behavior optimization; behavior synthesis; data-routing logic; discrete-register-based approach; distributed embedded memory blocks; distributed register file; distributed register-file microarchitecture; global interconnects; global-interconnections; inter-island connections; logic area reduction; multiplexing logic; multiplexors; on-chip memory; platform-based resource binding; register transfer level; register-file IP blocks; synthesis algorithms; Algorithm design and analysis; Computer science; Delay; Field programmable gate arrays; Integrated circuit interconnections; Integrated circuit synthesis; Logic; Microarchitecture; Permission; Registers; Behavior Synthesis; distributed register file; resource binding;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 2006. ICCAD '06. IEEE/ACM International Conference on
Conference_Location :
San Jose, CA
ISSN :
1092-3152
Print_ISBN :
1-59593-389-1
Electronic_ISBN :
1092-3152
Type :
conf
DOI :
10.1109/ICCAD.2006.320017
Filename :
4110256
Link To Document :
بازگشت