Title :
Input sensitive high-level power analysis
Author :
Hezavei, J. ; Vijaykrishnan, N. ; Irwin, M.J. ; Kandemir, M. ; Duarte, D.
Author_Institution :
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
fDate :
6/23/1905 12:00:00 AM
Abstract :
An input sensitive table based power estimation technique is proposed. The proposed technique has been applied to different circuits and validated using circuit-level simulation for 0.25 μm, 2.5 V CMOS technology. It is observed that the proposed scheme achieves an average error margin of 3.2% as compared to HSPICE, while running 27 times faster
Keywords :
CMOS logic circuits; SPICE; VLSI; circuit simulation; hardware description languages; 0.25 micron; 2.5 V; CMOS technology; HSPICE; NOR/NAND gates; VHDL cell libraries; VLSI systems; XOR gates; adders; average error margin; basic cell; circuit-level simulation; input sensitive high-level power analysis; input sensitive table based power estimation; multiplier; zero-detectors; CMOS technology; Circuit simulation; Computer science; Design engineering; Energy consumption; Power dissipation; Power engineering and energy; State estimation; Statistics; Switching circuits;
Conference_Titel :
Signal Processing Systems, 2001 IEEE Workshop on
Conference_Location :
Antwerp
Print_ISBN :
0-7803-7145-3
DOI :
10.1109/SIPS.2001.957341
