DocumentCode :
1652909
Title :
Physical planning for on-chip multiprocessor networks and switch fabrics
Author :
Ye, Terry Tao ; De Micheli, Giovanni
Author_Institution :
Comput. Syst. Lab., Stanford Univ., CA, USA
fYear :
2003
Firstpage :
97
Lastpage :
107
Abstract :
On-chip implementation of multiprocessor systems requires the planarization of the interconnect network onto the silicon floorplan. Manual floorplanning approaches will become increasingly more difficult and ineffective as multiprocessor complexity increases. Compared with traditional ASIC architectures, multiprocessors have homogeneous processing elements and regular network topologies. Therefore, traditional ASIC floorplanning methodologies based on macro placement are not effective in this domain. We propose an automated physical planning tool, called REGULAY, which can generate floorplans for different topologies under different design constraints. Compared with traditional floorplanning approaches, REGULAY shows significant advantages in reducing the total interconnect wire-length while preserving the regularity and hierarchy of the network topology.
Keywords :
circuit layout CAD; multiprocessing systems; multistage interconnection networks; network topology; system-on-chip; ASIC architecture; MPSoC; REGULAY; automated physical planning tool; homogeneous processing element; interconnect network; multiprocessor systems on chip; network topology; silicon floorplan; switch fabric; Computer networks; Energy consumption; Fabrics; Integrated circuit interconnections; Network topology; Network-on-a-chip; Planarization; Power system interconnection; Switches; Tiles;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Application-Specific Systems, Architectures, and Processors, 2003. Proceedings. IEEE International Conference on
ISSN :
2160-0511
Print_ISBN :
0-7695-1992-X
Type :
conf
DOI :
10.1109/ASAP.2003.1212833
Filename :
1212833
Link To Document :
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