Impact of cache optimization techniques on energy management

Due to the wide spread of mobile computing, and as we approach the scaling limits in CMOS circuits, issues such as heat dissipation and power management are emerging as critical aspects in memory systems design. Microprocessors, typically, come with one or more levels of cache. Caches are geared toward extremely high throughput and fast switching, thereby require great attention in power management to avoid malfunction or performance degradation. Historically, architectural alternatives had aimed at improving cache performance by reducing the miss rates, the miss penalties, and the time to hit the cache. These alternatives include techniques such as increasing the data block size, use of victim caches, higher associativity and, of course, compiler optimization. We examine the impact of these techniques on the energy requirements of the memory system. Each performance optimization technique is analyzed in relation to how it impacts the overall energy dissipation of the memory system. We use two measures - average-memory-access-time (AAMT), which is the average latency per memory reference; average-memory-access-energy (AMAE), which is the average energy dissipated per memory reference - to investigate performance and power tradeoffs for each optimization technique.