• DocumentCode
    1653361
  • Title

    A family of parallel-prefix modulo 2n-1 adders

  • Author

    Dimitrakopoulos, G. ; Vergos, H.T. ; Nikolos, D. ; Efstathiou, C.

  • Author_Institution
    Dept. of Comput. Eng. & Informatics, Patras Univ., Greece
  • fYear
    2003
  • Firstpage
    326
  • Lastpage
    336
  • Abstract
    We reveal the cyclic nature of idempotency in the case of modulo 2n-1 addition. Then based on this property, we derive for each n, a family of minimum logic depth modulo 2n-1 adders, which allows several trade-offs between the number of operators, the internal wire length, and the fanout of internal nodes. Performance data, gathered using static CMOS implementations, reveal that the proposed architectures outperform all previously reported ones in terms of area and/or operation speed.
  • Keywords
    adders; parallel architectures; performance evaluation; area; idempotency; internal node fanout; internal wire length; minimum logic depth modulo 2n - 1 adders; modulo addition; operation speed; operators; parallel architecture; parallel-prefix modulo 2n - 1 adders; performance data; static CMOS implementation; Bismuth; Computer errors; Computer networks; Concurrent computing; Fault tolerant systems; Floating-point arithmetic; IP networks; Logic; Power dissipation; TCPIP;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Application-Specific Systems, Architectures, and Processors, 2003. Proceedings. IEEE International Conference on
  • ISSN
    2160-0511
  • Print_ISBN
    0-7695-1992-X
  • Type

    conf

  • DOI
    10.1109/ASAP.2003.1212856
  • Filename
    1212856
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1653361