Title :
Scaling deep trench based eDRAM on SOI to 32nm and Beyond
Author :
Wang, G. ; Anand, D. ; Butt, N. ; Cestero, A. ; Chudzik, M. ; Ervin, J. ; Fang, S. ; Freeman, G. ; Ho, H. ; Khan, B. ; Kim, B. ; Kong, W. ; Krishnan, R. ; Krishnan, S. ; Kwon, O. ; Liu, J. ; McStay, K. ; Nelson, E. ; Nummy, K. ; Parries, P. ; Sim, J. ; Ta
Author_Institution :
Semicond. R&D Center, IBM, Hopewell Junction, NY, USA
Abstract :
A high performance embedded DRAM with deep trench capacitor and high performance SOI logic has been deployed in 45nm and 32nm technology nodes. Following a yield ramp of the sub-2ns latency 45nm technology, we present, for the first time, a 32nm eDRAM technology fully compatible with high performance logic with high-¿ metal gate access transistor and high-¿ node dielectric for the deep trench storage capacitor. We also describe the technology advancements required to scale the deep trench as well as the access transistor for optimal cell retention and performance. A clear scaling path is seen for the 22nm technology node.
Keywords :
DRAM chips; capacitors; embedded systems; high-k dielectric thin films; isolation technology; nanotechnology; silicon-on-insulator; SOI; deep trench capacitor; deep trench scaling; deep trench storage capacitor; eDRAM; embedded DRAM; high-¿ metal gate access transistor; high-¿ node dielectric; size 32 nm; size 45 nm; Capacitance; Capacitors; Dielectrics; Doping; Logic; Random access memory; Resource description framework; Space technology; Transistors; Wet etching;
Conference_Titel :
Electron Devices Meeting (IEDM), 2009 IEEE International
Conference_Location :
Baltimore, MD
Print_ISBN :
978-1-4244-5639-0
Electronic_ISBN :
978-1-4244-5640-6
DOI :
10.1109/IEDM.2009.5424375
