Title :
A fast analog circuit yield estimation method for medium and high dimensional problems
Author :
Liu, Bo ; Messaoudi, Jarir ; Gielen, Georges
Author_Institution :
ESAT-MICAS, Katholieke Univ. Leuven, Leuven, Belgium
Abstract :
Yield estimation for analog integrated circuits remains a time-consuming operation in variation-aware sizing. State-of-the-art statistical methods such as ranking-integrated Quasi-Monte-Carlo (QMC), suffer from performance degradation if the number of effective variables is large (as typically is the case for realistic analog circuits). To address this problem, a new method, called AYLeSS, is proposed to estimate the yield of analog circuits by introducing Latin Supercube Sampling (LSS) technique from the computational statistics field. Firstly, a partitioning method is proposed for analog circuits, whose purpose is to appropriately partition the process variation variables into low-dimensional sub-groups fitting for LSS sampling. Then, randomized QMC is used in each sub-group. In addition, the way to randomize the run order of samples in Latin Hypercube Sampling (LHS) is used for the QMC sub-groups. AYLeSS is tested on 4 designs of 2 example circuits in 0.35μm and 90nm technologies with yield from about 50% to 90%. Experimental results show that AYLeSS has approximately a 2 times speed enhancement compared with the best state-of-the-art method.
Keywords :
Monte Carlo methods; analogue integrated circuits; differential amplifiers; integrated circuit testing; integrated circuit yield; random processes; sampling methods; AYLeSS method; LSS sampling; Latin hypercube sampling; Latin supercube sampling technique; analog integrated circuits; computational statistics; fast analog circuit yield estimation method; high dimensional problems; low-dimensional subgroup fitting; medium dimensional problems; partitioning method; performance degradation; process variation variables; randomized QMC; ranking-integrated quasiMonte Carlo methods; size 0.35 mum; size 90 nm; statistical methods; variation-aware sizing; Accuracy; Analog circuits; Convergence; Design methodology; Fitting; Transistors; Yield estimation; Latin Supercube Sampling (LSS); Yield estimation; analog circuits;
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012
Conference_Location :
Dresden
Print_ISBN :
978-1-4577-2145-8
DOI :
10.1109/DATE.2012.6176569