1653388

Effects of optimized nitrogen tailoring in high-k dielectrics on impurity penetration and stress induced device degradation

Kang, Y. ; Rhee, S.J. ; Choi, C.H. ; Akvar, M.S. ; Kim, H.S. ; Zhang, M. ; Lee, T. ; Ok, I. ; Zhu, F. ; Lee, J.C.

Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA

2005

628

629

MOSFET; dielectric thin films; diffusion barriers; electron traps; hafnium compounds; hole traps; nitrogen; HfSiON; MOSFET; bottom interface layer quality; dielectric charge trapping; gate electrode impurity penetration; high-k gate dielectrics; layer thickness control; metallic impurity penetration blocking; optimized nitrogen tailoring; stress induced device degradation; time-dependent threshold voltage instability; top interface nitrogen-incorporation; Channel bank filters; Degradation; Electrodes; Hafnium; High-K gate dielectrics; Impurities; MOSFETs; Nitrogen; Sputtering; Stress;

English

ieee

Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. 2005 IEEE International

0-7803-8803-8

conf

10.1109/RELPHY.2005.1493176

1493176