Reconfigurable Viterbi decoding using a new ACS pipelining technique

A novel reconfigurable Viterbi decoder is proposed, based on an area-efficient ACS architecture, in which the constraint length and traceback depth can be on-line reconfigurable to trade-off decoding capability and decoding speed. Key techniques of the decoder are 5-level ACS (add-compare-select) pipelining and in-place path metric updating, which result in very high decoding speed and low memory usage. To verify the performance of the decoder, an example design with constraint length 7 to 10, has been successfully implemented on Xilinx Virtex FPGA devices. FPGA implementation results, in terms of decoding speed, resource usages and BER, have been obtained. These confirmed the functionality and the expected higher speeds and lower resources.