Title :
A low-power coarse-fine time-to-digital converter in 65nm CMOS
Author :
Xue-Jiao Zhang ; Ke-Ji Cui ; Zhuo Zou ; Li-Rong Zheng
Author_Institution :
Sch. of Inf. Sci. & Technol., Fudan Univ., Shanghai, China
Abstract :
A low-power coarse-fine time-to-digital converter (TDC) with a wide dynamic range and high time resolution is presented in this paper. The first stage is based on a buffer delay-line chain. Then the input signal and its adjacent reference clock are injected into a Vernier-delay-line (VDL) time-quantizer at the second stage for a finer resolution. The proposed architecture can provide high resolution with less hardware compared to the one-stage VDL TDC with the same dynamic range. A power-saving circuit is employed achieving >50% power reduction. A delay-tunable buffer is utilized to tolerate the process, voltage and temperature (PVT) variations. The design´s parameter has been simulated and optimized in a 65nm CMOS process. The simulation results show a minimum time resolution of 6.15 ps and a maximum dynamic range of 1260 ps corresponding to 8bits resolution. The power consumption is 2.5 mW with the reference frequency of 40MHz.
Keywords :
CMOS integrated circuits; buffer circuits; circuit tuning; clocks; delay lines; low-power electronics; power consumption; reference circuits; time-digital conversion; CMOS; PVT variation; TDC; VDL time-quantizer; Vernier-delay-line; buffer delayline chain; complementary metal oxide semiconductor; delay-tunable buffer; dynamic range; frequency 40 MHz; low-power coarse-fine time-to-digital converter; power 2.5 mW; power consumption; power reduction; power saving circuit; process voltage and temperature variation; reference clock; size 65 nm; time resolution; Delays; Detectors; Dynamic range; Image edge detection; Logic gates; Phase locked loops; Signal resolution;
Conference_Titel :
Signals, Circuits and Systems (ISSCS), 2015 International Symposium on
Conference_Location :
Iasi
Print_ISBN :
978-1-4673-7487-3
DOI :
10.1109/ISSCS.2015.7203992
