DocumentCode
1653550
Title
ITRS 2011 Analog EDA Challenges and Approaches
Author
Graeb, Helmut
Author_Institution
Dept. of Electr. Eng. & Inf. Technol., Tech. Univ. Munchen, Munich, Germany
fYear
2012
Firstpage
1150
Lastpage
1155
Abstract
In its recent 2011 version, The International Technology Roadmap for Semiconductors [1] updated a section on analog design technology challenges. In the paper at hand, these challenges and exemplary solution approaches will be sketched. In detail, structure and symmetry analysis, analog placement, design for aging, discrete sizing, sizing with in-loop layout, and performance space exploration will be touched.
Keywords
analogue integrated circuits; electronic design automation; integrated circuit layout; analog EDA; analog design technology; analog placement; discrete sizing; in-loop layout; performance space exploration; structure analysis; symmetry analysis; Aging; Algorithm design and analysis; Integrated circuit modeling; Layout; Optimization; Reliability; Transistors; Pareto; aging; analog design; layout; optimization; placement; reliability; sizing; synthesis; yield;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012
Conference_Location
Dresden
ISSN
1530-1591
Print_ISBN
978-1-4577-2145-8
Type
conf
DOI
10.1109/DATE.2012.6176575
Filename
6176575
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