A disturbance-free read scheme and a compact stochastic-spin-dynamics-based MTJ circuit model for Gb-scale SPRAM

Author

Ono, K. ; Kawahara, T. ; Takemura, R. ; Miura, K. ; Yamamoto, H. ; Yamanouchi, M. ; Hayakawa, J. ; Ito, K. ; Takahashi, H. ; Ikeda, S. ; Hasegawa, H. ; Matsuoka, H. ; Ohno, H.

Author_Institution

Central Res. Lab., Hitachi, Ltd., Tokyo, Japan

fYear

2009

Firstpage

1

Lastpage

4

Abstract

A magnetic-tunnel-junction (MTJ) circuit model, which considers spin dynamics under finite temperature, electrical bias, a stochastic process, and spin-transfer torque, was developed. Switching behaviors simulated by this model were verified by experimental measurements. Moreover, a disturbance-free read scheme for Gbit-scale spin-transfer torque RAM (SPRAM) was also developed. The feasibility of this scheme was confirmed by circuit simulation using the model and on-chip measurement of switching probability.

Keywords

MRAM devices; circuit simulation; magnetic tunnelling; spin dynamics; MTJ circuit model; circuit simulation; disturbance-free read scheme; spin-transfer torque RAM; stochastic-spin-dynamics; switching probability; Circuit simulation; Circuit testing; Laboratories; Magnetic circuits; Magnetic tunneling; Saturation magnetization; Semiconductor device modeling; Switching circuits; Torque; Tunneling magnetoresistance;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2009 IEEE International

Conference_Location

Baltimore, MD

Print_ISBN

978-1-4244-5639-0

Electronic_ISBN

978-1-4244-5640-6

Type

conf

DOI

10.1109/IEDM.2009.5424382

Filename

5424382