Title :
Parallel execution of the saturated reductions
Author :
De Dinechin, Benoît Dupont ; Monat, Christophe ; Rastello, Fabrice
Author_Institution :
STMicroelectron., Grenoble, France
fDate :
6/23/1905 12:00:00 AM
Abstract :
This paper addresses the problem of improving the execution performance of saturated reduction loops on fixed-point instruction-level parallel digital signal processors (DSPs). We first introduce "bit-exact" transformations, that are suitable for use in the ETSI and the ITU speech coding applications. We then present "approximate" transformations, the relative precision of which we are able to compare. Our main results rely on the properties of the saturated arithmetic
Keywords :
digital signal processing chips; fixed point arithmetic; parallel processing; speech coding; 32 bit; 4-MAC DSP; ETSI; ITU; accumulators; approximate parallel reductions; approximate transformations; bit-exact transformations; digital signal processors; execution performance; fixed-point instruction-level parallel DSP; multiply-accumulate instructions; parallel execution; saturated arithmetic; saturated reduction loops; speech coding applications; Arithmetic; Digital signal processing; Digital signal processors; Instruments; Internet telephony; Parallel processing; Signal generators; Signal processing algorithms; Speech coding; Telecommunication standards;
Conference_Titel :
Signal Processing Systems, 2001 IEEE Workshop on
Conference_Location :
Antwerp
Print_ISBN :
0-7803-7145-3
DOI :
10.1109/SIPS.2001.957365
