High performance low voltage amorphous oxide TFT Enhancement/Depletion inverter through uni-/bi-layer channel hybrid integration

Author

Yin, Huaxiang ; Kim, Sunil ; Park, Jaechul ; Song, Ihun ; Kim, Sang-Wook ; Hur, Jihyun ; Park, Sungho ; Jeon, Sanghun ; Kim, Chang Jung

Author_Institution

Semicond. Lab., Samsung Adv. Inst. of Technol., Yongin, South Korea

fYear

2009

Firstpage

1

Lastpage

4

Abstract

A novel amorphous oxide TFT Enhancement/Depletion (E/D) inverter through uni-/bi-layer channel hybrid integration with conventional process is demonstrated. The device´s threshold voltages (V_th) is strictly controlled and the fabrication technique is specially designed. Comparing to the reported high speed bootstrapped inverter, the output swing, switching voltage gain and noise margin of E/D inverter are greatly improved and only the ring oscillator´s speed is slightly degraded while with a small supply voltage of 5 V.

Keywords

amorphous semiconductors; logic gates; thin film transistors; amorphous oxide TFT enhancement-depletion inverter; bilayer channel hybrid integration; low voltage TFT; noise margin; ring oscillator speed; switching voltage gain; threshold voltages; unilayer channel hybrid integration; voltage 5 V; Amorphous materials; Circuit simulation; Doping; Logic circuits; Logic devices; Low voltage; MOS devices; Pulse inverters; Thin film transistors; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2009 IEEE International

Conference_Location

Baltimore, MD

Print_ISBN

978-1-4244-5639-0

Electronic_ISBN

978-1-4244-5640-6

Type

conf

DOI

10.1109/IEDM.2009.5424389

Filename

5424389