Title :
Interconnect scaling-the real limiter to high performance ULSI
Author_Institution :
Portland Technol. Development, Intel Corp., Hillsboro, OR, USA
Abstract :
Reducing interconnect pitch improves layout density, but degrades interconnect RC delay. Increasing metal aspect ratio (thickness/width) improves RC delay, but maximum benefits are achieved at an aspect ratio of ~2. Adding more interconnect layers improves density and performance, but practical limits are reached in just a few generations. New conductor and dielectric materials and improved circuit design techniques will be needed to meet future ULSI interconnect requirements
Keywords :
ULSI; delays; integrated circuit interconnections; integrated circuit layout; integrated circuit metallisation; Interconnect scaling; circuit design techniques; conductor and dielectric materials; dielectric materials; high performance ULSI; interconnect pitch reduction; Capacitance; Conducting materials; Conductivity; Degradation; Delay estimation; Dielectric materials; Equations; Integrated circuit interconnections; Integrated circuit modeling; Ultra large scale integration;
Conference_Titel :
Electron Devices Meeting, 1995. IEDM '95., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2700-4
DOI :
10.1109/IEDM.1995.499187
