Interconnect capacitances, crosstalk, and signal delay in vertically integrated circuits

The impact of the three-dimensional circuit structure in Vertically Integrated Circuits (VICs) on interconnect capacitances, crosstalk and signal delay is investigated based on measurements and simulations. In comparison with planar IC technologies, increased substrate coupling and reduced coupling capacitances between adjacent interconnection lines considerably improve the noise immunity for VICs with chiplayers fabricated in silicon-bulk technology. For thin-film silicon-on-insulator chiplayers, noise immunity can be assured through the integration of conductive layers between active chips. The reduced interconnection lengths at system level lead to decreased interconnect delays despite higher total interconnect capacitances