A novel five-photo-mask low-temperature polycrystalline-silicon CMOS structure

A novel five-mask low temperature polycrystalline silicon (LTPS) complementary metal oxide semiconductor (CMOS) structure was verified by manufacturing Thin Film Transistor (TFT) test samples using the proposed five-mask LTPS CMOS process. In integrating the five-mask CMOS structure, a selective contact barrier metal formation process was developed without additional photo mask steps to solve the issue of high contact resistance problem encountered inevitably in the contact between indium tin oxide ITO and doped poly-Si source/drain layers. The five-mask CMOS technology was also confirmed by manufacturing a five-mask CMOS panel to be acceptable for the active matrix liquid crystal display (AMLCD) application.