DocumentCode :
1653847
Title :
Method for endurance optimization of the HIMOSTM flash memory cell
Author :
Yao, Thierry ; Lowe, Antony ; Vermeulen, Tom ; Bellafiore, Nicola ; Van Houdt, Jan ; Wellekens, Dirk
Author_Institution :
Technol. R&D, AMI-Semicond. Belgium BVBA, Oudenaarde, Belgium
fYear :
2005
Firstpage :
662
Lastpage :
663
Keywords :
MOS memory circuits; electric charge; electric potential; flash memories; integrated circuit reliability; optimisation; semiconductor device reliability; temperature; MOS flash memory cell; detrapping rate; endurance optimization; negative oxide charge; ramped write pulse; source side injection flash EEPROM cells; split-gate structure; split-point charge formation; threshold voltage window closure; trapping rate; write/erase cycles; Acceleration; Charge measurement; Current measurement; Flash memory cells; Interleaved codes; Optimization methods; Temperature; Testing; Threshold voltage; Voltage measurement;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. 2005 IEEE International
Print_ISBN :
0-7803-8803-8
Type :
conf
DOI :
10.1109/RELPHY.2005.1493193
Filename :
1493193
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=1653847
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