• DocumentCode
    1653872
  • Title

    Low temperature, low resistivity sub-half micron via/interconnect structure using reaction of Al-alloys and germane

  • Author

    Joshi, R.V. ; Tejwani, M.

  • Author_Institution
    IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
  • fYear
    1995
  • Firstpage
    257
  • Lastpage
    260
  • Abstract
    This paper presents a novel, low cost, low temperature process for filling high aspect ratio vias/lines with Al-based alloys with improved damascene capability. This is achieved by reacting Germane (GeH4 ) at temperatures below 400°C with Al-Cu alloys deposited by conventional techniques which result in voids, gaps and poor filling. The technique practically imposes no limitation on filling high aspect ratio vias including undercuts. The low temperature provides capability to form multilevel homogeneous Al-alloy via/line structure by maintaining the resistance of underlying interconnects. The reliability data shows that Al-Cu-Ge via/interconnect structure deposited by this method is at least “1.5×” better electromigration life time (t50) to that of hot sputtered Al-Cu (deposited at 535°C) and almost “1.8×” to that of conventionally used CVD W stud/Al-Cu interconnect structure. The improvement in the reliability may be attributed to filling without voids high aspect ratio sub-half micron vias with low resistivity metal such as Al-Cu-Ge at temperatures well below 400°C. A lower sheet resistance of Al-Cu-Ge line is achieved by this method compared to high temperature deposition due to less Ti wetting layer and limited Titanium reaction with Al-Cu-Ge. The other important result is that it is possible to achieve “high via chain yields” of difficult to polish materials like Al-alloys using a “unique” polishing process
  • Keywords
    aluminium alloys; copper alloys; integrated circuit interconnections; integrated circuit metallisation; 0.5 micron; 400 C; Al-Cu; Al-alloys; GeH4; chain yield; damascene capability; electromigration lifetime; germane; low temperature process; multilevel structure; polishing; reliability; sheet resistance; sub-half micron via/interconnect structure; surface reaction; Conductivity; Contact resistance; Filling; Optical films; Sputter etching; Sputtering; Surface morphology; Temperature; Testing; Tin;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 1995. IEDM '95., International
  • Conference_Location
    Washington, DC
  • ISSN
    0163-1918
  • Print_ISBN
    0-7803-2700-4
  • Type

    conf

  • DOI
    10.1109/IEDM.1995.499191
  • Filename
    499191