A unified VLSI architecture for addition and multiplication in GF(2m)

Modular addition and multiplication are key operations in many cryptographic and coding systems. In this paper we present a unified VLSI architecture for addition and multiplication in finite fields GF (2^m) with polynomial representation. The multiplication is based on a bit-serial LSB first algorithm. The multiplier can operate over a large number of binary fields with an order up to 2^m. As the adder and multiplier share the same data-path, the hardware complexity of the proposed architecture is smaller than Arithmetic Logic Units (ALUs) with separated adders and multipliers. The obtained architecture is regular, modular and scalable beeing well suited for a VLSI implementation. Moreover a low hardware complexity/low power design can be obtained.