Efficient FPGA implementation of the DCD-RLS algorithm for stereo acoustic echo cancellation

The development of teleconferencing systems has allowed the communication using two acoustic channels (stereo configuration). The corresponding standard acoustic echo cancellation process requires four adaptive filters with a considerable usage of hardware resources. In this context, the dichotomous coordinate descent (DCD) - recursive least-squares (RLS) algorithm, using the widely linear (WL) model, was proposed as an efficient alternative to the classical RLS solution. In this paper, an efficient Field Programmable Gate Array (FPGA) implementation of the DCD-RLS method is presented, with attractive numerical properties and good performance.