Title :
A normally-off GaN FET with high threshold voltage uniformity using a novel piezo neutralization technique
Author :
Ota, K. ; Endo, K. ; Okamoto, Y. ; Ando, Y. ; Miyamoto, H. ; Shimawaki, H.
Author_Institution :
Nano Electron. Res. Labs., NEC Corp., Otsu, Japan
Abstract :
In this paper, we successfully demonstrate a recessed gate normally-off GaN FET on a silicon substrate with high threshold voltage (Vth) uniformity and low on-resistance. In order to realize high Vth uniformity, a novel Vth control technique is proposed, which we call ¿piezo neutralization technique¿. This technique includes a piezo neutralization (PNT) layer formed at the bottom of the gate recess. Since the PNT layer neutralizes the polarization charges under the gate, the Vth comes to be independent of the gate-to-channel span. The fabricated normally-off GaN FET with PNT structure exhibits an excellent Vth uniformity (¿(Vth) = 18 mV) and a state-of-the-art combination of the specific on-resistance (RonA = 500 m ¿ mm2) and the breakdown voltage (VB > 1000 V). The normally-off GaN FETs wtih PNT structure show great promise as power devices.
Keywords :
III-V semiconductors; etching; field effect transistors; gallium compounds; silicon; wide band gap semiconductors; GaN; Si; field effect transistors; gate recess; gate-to-channel span; piezo neutralization technique; polarization charges; threshold voltage uniformity; Aluminum gallium nitride; Buffer layers; Electrodes; FETs; Gallium nitride; Insulated gate bipolar transistors; Polarization; Silicon; Substrates; Threshold voltage;
Conference_Titel :
Electron Devices Meeting (IEDM), 2009 IEEE International
Conference_Location :
Baltimore, MD
Print_ISBN :
978-1-4244-5639-0
Electronic_ISBN :
978-1-4244-5640-6
DOI :
10.1109/IEDM.2009.5424398
