High data rate synchronizers operating at low speed

This paper presents a new technique which allows high baud rate with low operation speed of the synchronizer. This technique is based on parallel processing. What is done by only one clock operating at the baud rate can be done by two clocks operating only at half rate. By generalizing we propose versions of clock recovery circuits operating at the ratio 1/2ⁿ of the data rate. Thus we obtain circuits transmitting at very high data rate but operating at very low frequency. The proposed circuits which are transition sensitive (digital) are compared with the traditional level sensitive (analog)