DocumentCode
1654284
Title
Application of local design-for-reliability techniques for reducing wear-out degradation of CMOS combinational logic circuits
Author
Xuan, Xiangdong ; Chatterjee, Abhijit ; Singh, Adit D.
Author_Institution
Georgia Institute of Technology
fYear
2004
Firstpage
24
Lastpage
29
Keywords
CMOS logic circuits; Circuit optimization; Circuit simulation; Combinational circuits; Degradation; Electromigration; Hot carriers; Integrated circuit modeling; Propagation delay; Space technology;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2004. ETS 2004. Proceedings. Ninth IEEE European
Print_ISBN
0-7695-2119-3
Type
conf
DOI
10.1109/ETSYM.2004.1347593
Filename
1347593
Link To Document