1654361

Impact of substrate bias on p-MOSFET negative bias temperature instability

Kumar, P.B. ; Dalei, T.R. ; Varghese, D. ; Saha, D. ; Mahapatra, S. ; Alam, M.A.

Dept. of Electr. Eng., Indian Inst. of Technol., Mumbai, India

2005

700

701

MOSFET; hot carriers; impact ionisation; interface states; semiconductor device reliability; thermal stability; tunnelling; CMOS circuits; NBTI; SPICE models; TCAD models; accelerated aging tests; bulk trap generation; electron tunneling; gate bias; hot-hole generation; impact ionization; interface trap generation; negative bias temperature instability; nonzero substrate bias stress effects; oxide thickness; p-MOSFET reliability; threshold voltage; Analog computers; CMOS technology; Hot carriers; Impact ionization; MOSFET circuits; Negative bias temperature instability; Niobium compounds; Reliability engineering; Stress; Titanium compounds;

English

ieee

Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. 2005 IEEE International

0-7803-8803-8

conf

10.1109/RELPHY.2005.1493212

1493212