Efficient npn operation in high voltage NMOSFET for ESD robustness

Author

Duvvury, C. ; Briggs, D. ; Rodrigues, Jose ; Carvajal, F. ; Young, A. ; Redwine, D. ; Smayling, M.

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

fYear

1995

Firstpage

345

Lastpage

348

Abstract

This paper presents a design technique to achieve parasitic npn turn-on in a high voltage drain extended nMOS (DEnMOS) transistor under ESD conditions. Using the gate-coupled design technique, the overlap between the n^- drain and the gate is designed for optimum gate potential transient corresponding to maximum substrate current generation under ESD, which can subsequently lead to forward biasing of the substrate-source junction. This approach resulted in more than 6 kV of ESD level for a 600/5 μm DEnMOS device

Keywords

CMOS integrated circuits; electrostatic discharge; integrated circuit reliability; power MOSFET; power integrated circuits; protection; semiconductor device reliability; 6 kV; ESD robustness; HV drain extended NMOS transistor; design technique; gate-coupled design technique; high voltage NMOSFET; maximum substrate current generation; npn operation; optimum gate potential transient; Breakdown voltage; CMOS process; Dielectric substrates; Diodes; Electrostatic discharge; Instruments; MOS devices; MOSFET circuits; Power integrated circuits; Robustness;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1995. IEDM '95., International

Conference_Location

Washington, DC

ISSN

0163-1918

Print_ISBN

0-7803-2700-4

Type

conf

DOI

10.1109/IEDM.1995.499211

Filename

499211