High performance CMOS operational-amplifier

Author

Vallee, Richard E. ; El-Masry, Ezz I.

Author_Institution

Dept. of Electr. Eng., Tech. Univ. of Nova Scotia, Halifax, NS, Canada

fYear

1989

Firstpage

1475

Abstract

The design of a high-performance CMOS operational-amplifier (op-amp) in 3-μm double-level-metal technology is presented. The amplifier makes use of stacked (cascode) current source techniques and an enhanced push-pull output stage. This op-amp will be used for the realization of high-frequency switched-capacitor (SC) filters. SPICE simulations of the op-amp show a unity gain bandwidth of 40 MHz and a DC gain of 72 dB when using a bias current of 100 μA and a load capacitance of 15 pF. A test chip implementing the op-amp and other analog test cells was fabricated. Test results from the fabricated device demonstrate a DC gain of about 67 dB, with a unity gain bandwidth of about 40 MHz and a 36 V/μs slew rate when using a bias current of about 100 μA and a 15-pF load

Keywords

CMOS integrated circuits; linear integrated circuits; operational amplifiers; 100 muA; 15 pF; 40 MHz; 67 to 72 dB; CMOS operational-amplifier; DC gain; SPICE simulations; analog test cells; bias current; double-level-metal technology; high-performance; linear IC; load capacitance; op-amp; push-pull output stage; switched-capacitor; unity gain bandwidth; Bandwidth; CMOS technology; Capacitance; Circuits; Clocks; Filters; Frequency; Mirrors; Operational amplifiers; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1989., IEEE International Symposium on

Conference_Location

Portland, OR

Type

conf

DOI

10.1109/ISCAS.1989.100636

Filename

100636