VLSI implementation of CRC-32 for 10 Gigabit Ethernet

Author

Henriksson, Tomas ; Eriksson, Henrik ; Nordqvist, Ulf ; Larsson-Edefors, Per ; Liu, Dake

Author_Institution

Dept. of Phys. & Meas. Technol., Linkoping Univ., Sweden

Volume

3

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

1215

Abstract

For 10 Gigabit Ethernet a CRC-32 generation is essential and timing critical. Many efficient software algorithms have been proposed for CRC generation. In this work we use an algorithm based on the properties of Galois fields, which gives very efficient hardware. The CRC generator has been implemented and simulated in both standard cells and a full-custom design technique. In standard cells from the UMC 0.18 micron library a throughput of 8.7 Gb/s has been achieved. In the full-custom design for AMS 0.35 micron process we have achieved a throughput of 5.0 Gb/s. The conclusion, based on extrapolation of device characteristics, is that CRC-32 generation for 10 Gb/s can be designed with standard cells in a 0.15 micron process technology, or using full-custom design techniques in a 0.18 micron process technology

Keywords

Galois fields; VLSI; application specific integrated circuits; cellular arrays; cyclic codes; local area networks; redundancy; 0.15 micron; 0.18 micron; 0.35 micron; 10 Gbit/s; 10 Gigabit Ethernet; 5.0 Gbit/s; 8.7 Gbit/s; CRC-32 generation; Galois field; VLSI circuit; full-custom design; software algorithm; standard cell; Cyclic redundancy check; Ethernet networks; Extrapolation; Galois fields; Hardware; Libraries; Software algorithms; Throughput; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957433

Filename

957433