Title :
3D 65nm CMOS with 320°C microwave dopant activation
Author :
Lee, Yao-Jen ; Lu, Yu-Lun ; Hsueh, Fu-Kuo ; Huang, Kuo-Chin ; Wan, Chia-Chen ; Cheng, Tz-Yen ; Han, Ming-Hung ; Kowalski, Jeff M. ; Kowalski, Jeff E. ; Heh, Dawei ; Chuang, Hsi-Ta ; Li, Yiming ; Chao, Tien-Sheng ; Wu, Ching-Yi ; Yang, Fu-Liang
Author_Institution :
Nat. Nano Device Labs., Hsinchu, Taiwan
Abstract :
For the first time, CMOS TFTs of 65 nm channel length have been demonstrated by using a novel microwave dopant activation technique. A low temperature microwave anneal is demonstrated and discussed in this study. We have successfully activated the poly-Si gate electrode and source/drain junctions, BF2 for p-MOS TFTs and P31 for n-MOS TFTs at a low temperature of 320°C without diffusion. The technology is promising for high performance and low cost upper layer nanometer-scale transistors as required by low temperature 3D-ICs fabrication.
Keywords :
CMOS integrated circuits; MOSFET; microwave devices; nanostructured materials; semiconductor doping; semiconductor junctions; thin film transistors; 3D-ICs fabrication; CMOS TFT; channel length; low temperature microwave anneal; microwave dopant activation technique; n-MOS TFT; nanometer-scale transistors; p-MOS TFT; poly-Si gate electrode; size 65 nm; source/drain junctions; temperature 320 C; Annealing; Costs; Electromagnetic heating; Fabrication; Heat transfer; Integrated circuit interconnections; Microwave devices; Microwave theory and techniques; Temperature; Thin film transistors;
Conference_Titel :
Electron Devices Meeting (IEDM), 2009 IEEE International
Conference_Location :
Baltimore, MD
Print_ISBN :
978-1-4244-5639-0
Electronic_ISBN :
978-1-4244-5640-6
DOI :
10.1109/IEDM.2009.5424426
