VLSI implementation for low density parity check decoder

In this paper, a low complexity digital Low Density Parity Check (LDPC) turbo code decoder architecture for real-time cellular personal communication application is presented. The proposed VLSI decoder architecture alleviates the use of complex operations such as combinational arithmetic, exponent computations and reduces intermediate storage as well as interleaving latency by incorporating an in-place algorithm, index look-up table and address counter. In addition, the output section and termination of iteration are implemented by simple decision logic. The entire decoder is designed and synthesized using the Synopsys VHDL computer aided design tool