Title :
Reconfigurable coprocessor based JPEG 2000 implementation
Author :
Martina, Maurizio ; Masera, Guido ; Piccinini, Gianluca ; Vacca, Fabrizio ; Zamboni, Maurizio
Author_Institution :
Dipt. di Elettronica, Politecnico di Torino, Italy
fDate :
6/23/1905 12:00:00 AM
Abstract :
This paper proposes a reconfigurable coprocessor based implementation for the forthcoming standard JPEG 2000 for still images. First a preliminary overview of the standard, mainly focusing on the major characteristics of the different functional units, is presented. Then results obtained by a profile analysis are shown and a partition between DSP and FPGA is proposed for the implementation of a codec architecture. Finally the most critical units in terms of required computation effort, have been mapped on FPGA devices in order to preserve an high degree of reconfigurability. It is worth noticing that to the best of our knowledge only software implementations of JPEG 2000 has been produced yet
Keywords :
VLSI; code standards; coprocessors; data compression; decoding; digital signal processing chips; entropy codes; field programmable gate arrays; image coding; image processing equipment; reconfigurable architectures; telecommunication standards; wavelet transforms; DSP; EBCOT processor core; FPGA; JPEG 2000 decoder; JPEG 2000 standard; TMS320C6201 DSP; VLSI architecture; XILINX Virtex device; block-based bitplane encoder; codec architecture; entropy encoding algorithm; functional units; image compression system; profile analysis; reconfigurable coprocessor; still images; wavelet processor; Coprocessors; Digital signal processing; Discrete wavelet transforms; Encoding; Field programmable gate arrays; Image coding; Kernel; Standards development; Tiles; Transform coding;
Conference_Titel :
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN :
0-7803-7057-0
DOI :
10.1109/ICECS.2001.957436
