Title :
A fast CRC implementation on FPGA using a pipelined architecture for the polynomial division
Author :
Monteiro, Fabrice ; Dandache, A. ; M´Sir, Amine ; Lepley, Bernard
Author_Institution :
SUPELEC, Metz Univ., France
fDate :
6/23/1905 12:00:00 AM
Abstract :
The CRC error detection is a very common function on telecommunication applications. The evolution towards increasing data rates requires more and more sophisticated implementations. In this paper, we present a method to implement the CRC function based on a pipeline structure for the polynomial division. It improves very effectively the speed performance, allowing data rates from 1 Gbit/s to 4 Gbit/s on FPGA implementations, according to the parallelisation level (8 to 32 bits)
Keywords :
digital communication; error detection codes; field programmable gate arrays; pipeline arithmetic; polynomials; 1 to 4 Gbit/s; 8 to 32 bit; CRC error detection; FPGA implementations; cyclic redundancy checking codes; fast CRC implementation; high data rates; pipelined architecture; polynomial division; speed performance; telecommunication applications; Circuits; Clocks; Cyclic redundancy check; Cyclic redundancy check codes; Field programmable gate arrays; Frequency; Pipeline processing; Polynomials; Protocols; Throughput;
Conference_Titel :
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN :
0-7803-7057-0
DOI :
10.1109/ICECS.2001.957437
