Performance and reliability optimization of ultrashort channel CMOS device for giga-bit DRAM applications

Author

Hwang, Hyunsang ; Youn, Kang-Sik ; Ahn, Jae-Gyung ; Yang, Dooyoung ; Ha, Jae-Hee ; Huh, Yun-Jun ; Park, Jin-Won ; Kim, Jae-Jeong ; Kim, Woo-Sik

Author_Institution

ULSI Lab., LG Semicon Co., Cheongju, South Korea

fYear

1995

Firstpage

435

Lastpage

438

Abstract

Extensive reliability and performance characteristics of ultrashort channel CMOS devices with various process conditions for giga-bit DRAM were investigated. Using conventional process with various oxide thicknesses and doping profiles, we fabricated 0.1 μm channel length n⁺ gate MOSFETs with excellent electrical characteristics. Based on these results, practical device design windows were proposed for 1.5 V operating bias. Considering significant improvement of hot carrier lifetime of ring-oscillator, hot-carrier reliability is not a major constraint for L_eff=0.1 μm at 1.5 V operating bias

Keywords

CMOS memory circuits; DRAM chips; MOSFET; carrier lifetime; doping profiles; hot carriers; integrated circuit reliability; semiconductor device reliability; 0.1 micron; 1.5 V; doping profiles; giga-bit DRAM applications; hot carrier lifetime; n⁺ gate MOSFETs; performance characteristics; reliability optimization; ultrashort channel CMOS device; CMOS process; Electric variables; Hot carriers; MOS capacitors; MOSFET circuits; Plasma measurements; Random access memory; Ring oscillators; Tunneling; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1995. IEDM '95., International

Conference_Location

Washington, DC

ISSN

0163-1918

Print_ISBN

0-7803-2700-4

Type

conf

DOI

10.1109/IEDM.1995.499232

Filename

499232