• DocumentCode
    1654998
  • Title

    Efficient Gröbner basis reductions for formal verification of galois field multipliers

  • Author

    Lv, Jinpeng ; Kalla, Priyank ; Enescu, Florian

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Utah, Salt Lake City, UT, USA
  • fYear
    2012
  • Firstpage
    899
  • Lastpage
    904
  • Abstract
    Galois field arithmetic finds application in many areas, such as cryptography, error correction codes, signal processing, etc. Multiplication lies at the core of most Galois field computations. This paper addresses the problem of formal verification of hardware implementations of (modulo) multipliers over Galois fields of the type F(2k), using a computer-algebra/algebraic-geometry based approach. The multiplier circuit is modeled as a polynomial system in F(2k)[x1, x2, ... , xd] and the verification problem is formulated as a membership test in a corresponding (radical) ideal. This requires the computation of a Gröbner basis, which can be computationally intensive. To overcome this limitation, we analyze the circuit topology and derive a term order to represent the polynomials. Subsequently, using the theory of Gröbner bases over Galois fields, we prove that this term order renders the set of polynomials itself a Gröbner basis of this ideal - thus significantly improving verification. Using our approach, we can verify the correctness of, and detect bugs in, upto 163-bit circuits in F(2163); whereas contemporary approaches are infeasible.
  • Keywords
    Galois fields; digital arithmetic; formal verification; multiplying circuits; network topology; polynomials; process algebra; 163-bit circuits; Galois field arithmetic; Galois field multiplier; Grobner basis reductions; algebraic geometry-based approach; bug detection; circuit topology; computer algebra-based approach; formal verification; multiplier circuit modeling; multiplier hardware implementation; polynomial system; Boolean functions; Computer bugs; Data structures; Elliptic curve cryptography; Integrated circuit modeling; Logic gates; Polynomials;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012
  • Conference_Location
    Dresden
  • ISSN
    1530-1591
  • Print_ISBN
    978-1-4577-2145-8
  • Type

    conf

  • DOI
    10.1109/DATE.2012.6176625
  • Filename
    6176625