DocumentCode
165503
Title
Iterative architecture for value iteration using memristors
Author
Ebong, I.E. ; Mazumder, P.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., Univ. of Michigan, Ann Arbor, MI, USA
fYear
2014
fDate
18-21 Aug. 2014
Firstpage
967
Lastpage
970
Abstract
Memristors promise higher device density and design flexibility. Besides utilizing memristors for digital memory, another promising avenue for adoption is the advancement of neural network circuits capable of learning. Neural network implementations with memristors have been proposed, including memristor synaptic training methodologies. This work highlights applications of a neural learning methodology inspired by Q-learning. Memristors are used as analog storage elements to store a large Q-table. The method is qualified with a maze problem in order to show that the proposed network can be used to learn to approximate an optimal path to solving the maze problem. Brief results highlighting the methodology on a maze problem and discussion on generating random keys are provided. This work combines model-free reinforcement learning with neural networks.
Keywords
analogue storage; iterative methods; learning (artificial intelligence); memristors; neural nets; Q-learning; Q-table; analog storage element; digital memory; iterative architecture; maze problem; memristor synaptic training methodology; model-free reinforcement learning; neural learning methodology; neural network circuit; random key generation; value iteration; Hardware; Mathematical model; Memristors; Neural networks; Neurons; Resistance; Training;
fLanguage
English
Publisher
ieee
Conference_Titel
Nanotechnology (IEEE-NANO), 2014 IEEE 14th International Conference on
Conference_Location
Toronto, ON
Type
conf
DOI
10.1109/NANO.2014.6967997
Filename
6967997
Link To Document