Novel contamination restrained silicidation processing using load-lock LPCVD-films and lightly doped deep drain (LD3) structure for deep submicron dual gate CMOS

A novel low leakage, low resistance and high temperature stability titanium salicide process named “Silicidation after ion Implantation through the Contamination-Restrained Oxygen free LPCVD-Nitride layer in a Lightly Doped diffusion layer (LD-SICRON)” has been developed. This novel LD-SICRON process has been successfully implemented in deep submicron dual gate CMOS development. Junction leakage current for TiSi₂-n⁺/p and -p⁺/n was reduced to the non-silicidation level (area component: 0.8~3.6 nA/cm², peripheral component: 3.1~3.6 pA/cm). Low sheet resistances of n⁺ - and p⁺-gate electrodes (4 Ω/square) were maintained below the 0.2 μm line even after high temperature annealing (1000°C, 10 sec+850°C, 30 min.)