A 10 b, 40 Msample/s, 25 mW pipeline analog to digital converter

Author

Amirabadi, Amir ; Tabrizi, M. Moghaddam ; Sharifkhani, Mohammad ; Shoaei, Omid

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Tehran, Iran

Volume

4

fYear

2004

Firstpage

1989

Abstract

This paper describes a 10 b pipelined ADC designed in 0.35 μm CMOS technology which achieves a power dissipation of 25 mW at full speed operation from a single 3 V supply. The proposed high speed gain-boosted operational amplifier make it possible to achieve requirements of 10-bit resolution and settling time of 8 ns within 0.01% accuracy. A dynamic comparator is used for power efficiency. This design achieves INL and DNL of 0.68 LSB and 0.45 LSB respectively, while SNDR is 58.2 dB and SFDR is 73.4.

Keywords

CMOS integrated circuits; analogue-digital conversion; comparators (circuits); operational amplifiers; pipeline processing; power consumption; 0.35 micron; 10 bit; 25 mW; 3 V; 8 ns; CMOS technology; dynamic comparator; gain-boosted operational amplifier; high speed operational amplifier; pipeline analog to digital converter; pipelined ADC; power dissipation; Analog-digital conversion; Capacitors; Design engineering; Error correction; Optical computing; Pipelines; Power dissipation; Power engineering and energy; Power engineering computing; Quantization;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2004. Canadian Conference on

ISSN

0840-7789

Print_ISBN

0-7803-8253-6

Type

conf

DOI

10.1109/CCECE.2004.1347618

Filename

1347618