Title :
Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values
Author :
Kajihara, Seiji ; Saluja, Kewal K. ; Reddy, Sudhakar M.
Author_Institution :
Kyushu Institute of Technology
Keywords :
Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Electrical fault detection; Electrons; Fault detection; Logic circuits; Logic testing; Sufficient conditions;
Conference_Titel :
Test Symposium, 2004. ETS 2004. Proceedings. Ninth IEEE European
Print_ISBN :
0-7695-2119-3
DOI :
10.1109/ETSYM.2004.1347620
