Fully planarized four-level interconnection with stacked vias using CMP of selective CVD-Al and insulator and its application to quarter micron gate array LSIs

Author

Amazawa, T. ; Yamamoto, E. ; Sakuma, K. ; Ito, Y. ; Kamoshida, K. ; Ikeda, K. ; Saito, K. ; Ishii, H. ; Kato, S. ; Yagi, S. ; Hiraoka, K. ; Ueki, T. ; Takeda, T. ; Arita, Y.

Author_Institution

NTT LSI Labs., Atsugi, Japan

fYear

1995

Firstpage

473

Lastpage

476

Abstract

The chemical mechanical polishing (CMP) of selective aluminum (Al) CVD via plugs is examined for the first time and a fully planarized four-level interconnection system with all stacked via plugs is demonstrated. A sandwich of Ti/TiN/Ti barrier layers with an Al-CVD plug has proved to be one of the best via plug structures because of its low via resistance and extremely high reliability. Quarter-micron 120-kG gate array LSIs have been successfully fabricated using a 1.4 μm, equal pitch, four-level interconnection

Keywords

CMOS digital integrated circuits; CVD coatings; SIMOX; VLSI; aluminium; electromigration; integrated circuit interconnections; integrated circuit reliability; polishing; titanium; titanium compounds; 0.25 mum; CMOS/SIMOX VLSI; CMP; Ti-TiN-Ti-Al; Ti/TiN/Ti barrier layers; chemical mechanical polishing; electromigration reliability; equal pitch four-level interconnection; fully planarized four-level interconnection system; gate array LSIs; high reliability; low via resistance; selective Al CVD via plugs; selective CVD-Al; stacked vias; Aluminum; Control systems; Etching; Indium tin oxide; Inductors; Insulation; Large scale integration; Plugs; Weight control; Yagi-Uda antennas;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1995. IEDM '95., International

Conference_Location

Washington, DC

ISSN

0163-1918

Print_ISBN

0-7803-2700-4

Type

conf

DOI

10.1109/IEDM.1995.499241

Filename

499241