Title :
“NET-AN” a full three-dimensional parasitic interconnect distributed RLC extractor for large full chip applications
Author :
Akcasu, Osman Ersed ; Lu, Jesse ; Dalal, Alexander ; Mitra, Sundari ; Lev, Lavi ; Vassegihi, N. ; Pance, Aleksandar ; Hingarh, Hem ; Basit, Haris
Author_Institution :
OEA Int. Inc., Santa Clara, CA, USA
Abstract :
A full 3D RLC extraction capability is presented which is suitable for very large nets on very large chips. The need, solution methodology, and usage in a real design environment are shown. The extracted parasitics and their effects on the delay/skew numbers are presented for real clock distribution circuits from real production designs, not test chips or special layouts
Keywords :
circuit layout CAD; delays; distributed parameter networks; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; 3D RLC extraction capability; NET-AN; delay/skew numbers; large full chip applications; logic block layout; real clock distribution circuits; real design environment; real production designs; solution methodology; three-dimensional parasitic interconnect distributed RLC extractor; very large chips; very large nets; Capacitance; Circuit testing; Clocks; Delay effects; Driver circuits; Geometry; Integrated circuit interconnections; Microprocessors; RLC circuits; Timing;
Conference_Titel :
Electron Devices Meeting, 1995. IEDM '95., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2700-4
DOI :
10.1109/IEDM.1995.499246
