ASIC implementations of five SHA-3 finalists

Author

Guo, Xu ; Srivastav, Meeta ; Huang, Sinan ; Ganta, Dinesh ; Henry, Michael B. ; Nazhandali, Leyla ; Schaumont, Patrick

Author_Institution

Bradley Dept. of Electr. & Comput. Eng., Virginia Tech, Blacksburg, VA, USA

fYear

2012

Firstpage

1006

Lastpage

1011

Abstract

Throughout the NIST SHA-3 competition, in relative order of importance, NIST considered the security, cost, and algorithm and implementation characteristics of a candidate [1]. Within the limited one-year security evaluation period for the five SHA-3 finalists, the cost and performance evaluation may put more weight in the selection of winner. This work contributes to the SHA-3 hardware evaluation by providing timely cost and performance results on the first SHA-3 ASIC in 0.13 μm IBM process using standard cell CMOS technology with measurements of all the five finalists using the latest Round 3 tweaks. This article describes the SHA-3 ASIC design from VLSI architecture implementation to the silicon realization.

Keywords

CMOS integrated circuits; VLSI; application specific integrated circuits; cryptography; elemental semiconductors; integrated circuit design; silicon; ASIC design; IBM process; NIST SHA-3 competition; National Institute of Standards and Technology; SHA-3 finalists; Si; VLSI architecture implementation; cryptographic hash function; hardware evaluation; one-year security evaluation period; performance evaluation; round 3 tweaks; standard cell CMOS technology; Application specific integrated circuits; CMOS integrated circuits; Clocks; Computer architecture; Hardware; Layout; Synchronization;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012

Conference_Location

Dresden

ISSN

1530-1591

Print_ISBN

978-1-4577-2145-8

Type

conf

DOI

10.1109/DATE.2012.6176643

Filename

6176643