An improved delay compensation technique for digital clock recovery loops

It is well known that time delays often cause instability in a closed-loop system forcing it to operate under sub-optimal conditions. Timing recovery systems encountered in today´s communications systems are an example of such systems due to the latency caused, on one side, by the always increasing data rate and, on the other, by the complexity of the signal processing employed. It is possible to modify the topology of a Phase Locked Loop (PLL) in order to reduce the effects that latency has on the loop stability and dynamics. This paper proposes a new topology which differs from previous work in that it is characterized by a closed-loop transfer function which is the product of a delay term and a rational function in z and, at the same time, achieves zero steady-state error in response to a frequency step