Asynchronous low power VLSI implementation of the International Data Encryption Algorithm

An asynchronous VLSI implementation of the International Data Encryption Algorithm (IDEA) is presented in this paper. In order to evaluate the asynchronous design, a synchronous version of the algorithm was also designed. The VHDL hardware description language was used in order to describe the algorithm. By using Synopsys commercially available tools, the VHDL code was synthesized. After placing and routing, both designs were fabricated with 0.6 μm CMOS technology. With a system clock of up to 8 MHz and a power supply of 5 V, the two chips were tested and evaluated, comparing them with the software implementation of the IDEA algorithm. This new approach proves efficiently the lower power consumption of the asynchronous implementation compared to the existing synchronous one. Therefore the asynchronous chip performs efficiently in WEP (Wireless Encryption Protocols) and high speed networks