• DocumentCode
    1655923
  • Title

    A design methodology to realize delay testable controllers using state transition information

  • Author

    Iwagaki, Tsuyoshi ; Ohtake, Satoshi ; Fujiwara, Hideo

  • Author_Institution
    Nara Institute of Science and Technology
  • fYear
    2004
  • Firstpage
    168
  • Lastpage
    173
  • Keywords
    Circuit faults; Circuit testing; Clocks; Delay effects; Design methodology; Electrical fault detection; Fault detection; Fault diagnosis; Logic testing; Performance evaluation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium, 2004. ETS 2004. Proceedings. Ninth IEEE European
  • Print_ISBN
    0-7695-2119-3
  • Type

    conf

  • DOI
    10.1109/ETSYM.2004.1347655
  • Filename
    1347655
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1655923