DocumentCode :
1655967
Title :
Static analysis of asynchronous clock domain crossings
Author :
Chaturvedi, Shubhyant
Author_Institution :
Adv. Micro Devices Inc., Austin, TX, USA
fYear :
2012
Firstpage :
1122
Lastpage :
1125
Abstract :
Clock domain crossing (CDC) signals pose unique and challenging issues in complex designs with multiple asynchronous clocks running at frequencies as high as multiple giga hertz. Designers can no longer rely on ad hoc approaches to CDC analysis. This paper describes a methodical approach for static analysis of structural issues in asynchronous CDCs. The illustrated approach can be integrated easily in standard static timing analysis (STA) flows of any design house. The methodology was successfully deployed on a 32 nm accelerated processing unit (APU) design, and a case study of the same is included in this paper.
Keywords :
asynchronous circuits; clocks; network synthesis; APU design; accelerated processing unit design; multiple asynchronous CDC signal analysis; multiple asynchronous clock domain crossing signal analysis; multiple giga hertz; size 32 nm; standard STA flow; standard static timing analysis flow; Clocks; Convergence; IP networks; Registers; Synchronization; System-on-a-chip; CDC; STA; clock domain crossing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012
Conference_Location :
Dresden
ISSN :
1530-1591
Print_ISBN :
978-1-4577-2145-8
Type :
conf
DOI :
10.1109/DATE.2012.6176664
Filename :
6176664
Link To Document :
بازگشت