DocumentCode
1655969
Title
An efficient scan tree design for test time reduction
Author
Bonhomme, Y. ; Yoneda, T. ; Fujiwara, H. ; Girard, P.
Author_Institution
Nara Institute of Science and Technology
fYear
2004
Firstpage
174
Lastpage
179
Keywords
Circuit testing; Computer architecture; Controllability; Design for testability; Encoding; Energy consumption; Information science; Observability; Switches; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2004. ETS 2004. Proceedings. Ninth IEEE European
Print_ISBN
0-7695-2119-3
Type
conf
DOI
10.1109/ETSYM.2004.1347657
Filename
1347657
Link To Document