Title :
An efficient scan tree design for test time reduction
Author :
Bonhomme, Y. ; Yoneda, T. ; Fujiwara, H. ; Girard, P.
Author_Institution :
Nara Institute of Science and Technology
Keywords :
Circuit testing; Computer architecture; Controllability; Design for testability; Encoding; Energy consumption; Information science; Observability; Switches; System-on-a-chip;
Conference_Titel :
Test Symposium, 2004. ETS 2004. Proceedings. Ninth IEEE European
Print_ISBN :
0-7695-2119-3
DOI :
10.1109/ETSYM.2004.1347657
