Maximum power supply noise estimation in VLSI circuits using multimodal genetic algorithms

This paper presents a genetic algorithm (GA) based method for finding the maximum voltage drop in the power bus of digital VLSI circuits. The worst-case voltage drop at a specified node in the power bus is defined as the fitness value for different input-vector pairs. A gate-level simulator and a sparse linear solver are applied to compute the fitness value. A sharing technique is applied to find the global optima accurately and rapidly. Comparisons with input-independent simulations for circuits extracted from layouts are used to validate our approach