A study and comparison of full adder cells based on the standard static CMOS logic

An overview of the performance of 1-bit full adder cells based on the main standard static logic styles and in depth examination of the advantages and limitations of each of them with respect to speed and power dissipation are presented. A comparison is performed in a wide range of main static logic styles. Six 1-bit full adder circuits based on these logic styles are chosen for the extensive evaluation. These circuits were redesigned at the transistor-level in a standard 0.18 μm CMOS process technology and comparison reported here uses HSPICE simulations to assess their performance. Realistic circuit arrangements are used to demonstrate the performance of each 1-bit full adder cell. The work presented in this paper gives a quantitative comparison of the adder cell performance. The results rearranged the previous full adder cell ranking.